Semiconductor devices are typically fabricated using a process that involves a number of sequential process steps. Each step in the sequence represents an additional expense for the overall manufacturing process, and therefore there is consistently a need for new methods that can make the fabrication of the semiconductor devices more efficient, without sacrificing the quality and reliability of the resulting devices. This is especially the case in the recent past, as market demands have pushed for smaller and more compact components that nevertheless have more functionality than previous designs.
A semiconductor device, generally speaking, is an electrical component, or set of components, fabricated onto a substrate that is made of a semiconductor material such as silicon. Examples of such devices include diodes, capacitors, transistors, and combinations of these basic components. In most modern semiconductor devices, a great many very small components are fabricated onto a wafer. A wafer is a thin, usually circular slice of semiconductor material that is used as a substrate for fabrication. The wafer in most cases is divided up into a number of dice, which after fabrication will be separated and packaged for individual use. Each die, after packaging, will form a component part of an electrical appliance such as a personal computer, a cellular telephone, or a personal digital assistant. These individual component parts are often called chips. Many recently-developed chips may even contain multiple dice, with each die performing its own function either independently or in cooperation with the others. In order to accomplish these functions, the individual semiconductor devices formed on each chip are interconnected to form integrated circuits (ICs). Access points such as bond pads are available on each die for terminating the leads or wires to connect the ICs on the chip with other, external components of the electrical appliance where the chip is installed.
To begin the manufacture of a semiconductor device, a thin slice of silicon or other suitable material is formed from an ingot. Selectively implanting areas on the surface of this wafer substrate with impurities such as boron or phosphorous ions give portions of the silicon wafer their semiconducting properties. These properties are, of course, very important to the operation of the device. In a transistor, for example, a source region and a drain region are formed in a spaced apart relationship at the surface of the substrate in this manner. The space between the source region and the drain region is called a channel, and an electrical current may flow through the channel under certain conditions. In the case of a transistor, a gate placed over the channel is electrically charged in order to start the flow of electrical current.
The gate, generally speaking, is formed of a conductive gate electrode that is separated from the channel region by a thin layer of dielectric material, often referred to as the gate dielectric. An example is shown in FIG. 1. FIG. 1 is a side (elevation) view illustrating in cross-section an exemplary transistor 10. Transistor 10 includes a gate structure 11, which is formed on substrate 12. Gate structure 11 includes gate electrode 15, which is separated from substrate 12 by gate dielectric 14. Disposed above the gate electrode 15 is a contact region 16, through which reliable electrical connections may be made. In many applications, gate electrode 15 is made of a poly (polycrystalline silicon) material and contact region 16 is formed of a metal such as gold or copper. On either side of the gate structure 11 is a spacer 17 to protect the gate electrode physically and electrically, and also to aid in the proper creation of the source and drain regions. On one side and adjacent to the gate structure 11, a source region 18 has been formed in the substrate 12. On the other side and adjacent to the gate structure 11 a drain region 19 has also been formed in substrate 12. Channel 20 is the substrate region disposed between source region 18 and drain region 19. Electrical contacts 21 and 22 have been formed on source region 18 and drain region 19, respectively.
To form a semiconductor device such as transistor 10 illustrated in FIG. 1, layers of insulating and conductive material are sequentially formed on either the substrate or previously-formed layers. Each layer may be selectively etched away to form the structures needed for the fabrication of each separate component. Naturally, a large number of such components may be fabricated at the same time. Selective etching, or other types of material removal, may be performed by exposing certain regions of the wafer to an appropriate solvent or other removal mechanism for a predetermined amount of time. During etching, regions that are to remain may be protected by a structure that is resistant to the removal process being implemented at that stage. This protective process is often called photolithography, and the resistant structure is made of a material called photoresist. The photoresist is normally formed into a single layer that is then patterned into individual structures. This may be achieved by selectively exposing the photoresist to light energy at certain frequency and intensity. This exposure causes a physical change in either the exposed or unexposed portions of the photoresist (depending on the type used), and the undesired photoresist regions may then be washed away by a solvent. After the etching process is complete, the remaining photoresist may be removed by another solvent selected for its capability to perform this function. The photoresist structures may also be removed by a process called ashing, which involves dissolving the photoresist by oxidation.
An example fabrication process is shown in FIG. 2. FIG. 2 is a flow diagram illustrating an exemplary method 30 of fabricating a semiconductor device, in this case the transistor 10 shown in FIG. 1. At START it is assumed that all materials and equipment necessary for performing the method are available and operational. The method begins with forming an oxide layer on the substrate (step 32). A poly layer for the gate electrode is then formed (step 34) as well. A photoresist layer is then formed (step 36) and patterned (step 38) so that a photoresist structure protects the region where the gate structure will be formed. An etching step is now performed (step 40), leaving the gate structure of the substrate, and the remaining photoresist removed (step 42). The source region and the drain region may now be partially formed by ion implantation (step 44), sometimes called doping, in many cases after adding additional temporary or permanent protective structures (step not shown).
In this exemplary method, a dielectric layer is then deposited (step 46) and selectively etched (step 48) to form the spacers for the gate structure. An additional ion implantation (step 50) forms the deeper part of the source region and drain region according to the process this example (see FIG. 1). An electrical contact region may then be formed on top of the gate electrode at this time (step 52), although the individual steps that may be involved are not separately shown in FIG. 2. At this point the transistor 10 has been formed and fabrication may continue with the addition of additional material layers and the formation of additional devices.
Naturally, FIG. 2 represents only one of many ways of forming transistors and similar devices. Fabrication techniques and materials have increased in sophistication in recent years. These advances have often been made necessary by the drive for making ever-smaller devices. At times these more sophisticated techniques and new materials are needed to make fabrication of such tiny devices feasible, and at other times they are necessary to make the devices function as intended. Expense is also an issue, and improvements are needed so that even more capable devices can be made at a lower cost.
New components have also been developed for these reasons, that is, to aid in the fabrication process, to reduce expense, and to improve the capabilities of the device for which they are ultimately to be a component part. One such innovation is a CMOS (complementary metal oxide semiconductor) device. A CMOS device includes two types of transistors that work together. Although similar in structure, the NMOS transistor and the PMOS transistor that make up a CMOS device are slightly different in composition. This can pose a challenge during fabrication, where identical or nearly identical devices contribute to manufacturing efficiencies that are lost when the differentiation between neighboring components must be achieved.
One such device is illustrated in FIG. 3. FIG. 3 is a side view illustrating in cross-section an exemplary CMOS semiconductor device 100. Semiconductor device 100 has two gates, including one associated with NMOS device 110 and one associated with PMOS device 150. Exemplary CMOS device 100 is formed on a substrate 101, which in this case is a p-doped silicon substrate. For this reason an n-well 102 has been formed in substrate 101 to accommodate the PMOS device 150. Isolation structure 104 separates the PMOS device 150 from the NMOS device 110, and isolation structures 103 and 105 separate a respective one of these devices from others (not shown) adjacent to them. Note that although only a single CMOS device is shown in FIG. 3, there are likely to be a great many of them disposed on the substrate, usually in addition to other types of devices as well.
In this example, NMOS device 110 includes a gate structure 120 formed on the substrate 101. Adjacent to and on respective opposing sides of gate structure 120 are source region 112 and drain region 114, also formed in the substrate 101, defining channel 113. The NMOS gate structure 120, disposed over channel 113, includes a gate electrode 124 that is physically separated from the substrate 101 by a gate oxide 122 (sometimes referred to as an oxide layer within the gate structure 120). Spacers 126 and 127 are formed on either side of the gate structure 120, are frequently formed of an oxide material but could include a nitride as well. Contact 129 is formed atop gate electrode 124 and facilitates electrical connections to it.
Similarly, PMOS device 150 of CMOS device 100 features a PMOS gate structure 160 disposed over n-well 102 of substrate 101. On either side of gate structure 160 is disposed, respectively; source 152 and drain 154, which together define channel 153. The gate structure 160 includes a gate electrode 164 that is physically separated from n-well 102 by an oxide layer 162. Spacers 166 and 167 are formed on either side of gate structure 160, and contact 169 is formed atop gate electrode 164. The source and drain regions of CMOS device 100 are also accessed electrically through contacts of metal or some other conductor. Contact 130 is formed over the source region 112 of NMOS device 110, and in this example is connected to ground. Contact 170 similarly is disposed over drain region 154 of PMOS device 150, and connects it to a positive voltage source. Contact 180, disposed above isolation structure 104 is in contact with both the drain region 114 of NMOS device 110 and with the source region 152 of PMOS device 150, enabling device 100 to function as a CMOS device.
The fabrication process for CMOS device 100 is similar though not identical to that described above in reference to FIG. 2. Note that both of the gates structures 120 and 160 appear in FIG. 3 to be nearly identical, which may in fact be the case in some applications. In many recent applications, however, it has been found that overall improvement may be obtained by modifying only one of the two devices (from the configuration shown in FIG. 3), or by modifying both of them, but in different ways. As should be apparent, this may pose additional challenges in the fabrication process. Some modifications, for example, may be beneficial when used in PMOS devices, but detrimental in NMOS devices. Similar considerations arise in other applications where two (or more) different structures must be formed. The challenge arises to manufacture both devices in a dual-gate semiconductor device to accommodate these differences without having to make each of the different devices in a completely separate sequence of steps. Needed then is a method for creating dual-gate semiconductor devices efficiently. The present invention provides just such a solution.